It is known in the art to provide a segmented or dual digital-to-analog converter wherein a resistive voltage divider provides a coarse conversion by means of switches controlled by a decoder from the more significant bits of a digital signal and a further, fine voltage divider provides a fine conversion in response to the less significant bits of the digital signal. The use of a coarse (M-bit) converter cascaded with a fine (L-bit) converter instead of a N-bit converter (wherein N=M+L) produces a very great saving in the number of devices which are required for the conversion and accordingly a very great saving in the area of the converter. Usually a N-bit converter requires 2.sup.N accurate devices whereas a cascaded converter needs only (2.sup.M +2.sup.L) such devices.
Post et al., in ESSCIRC 82, pages 69 to 72, describe a 14 bit monotonic NMOS digital-to-analog converter in which two ladder networks are arranged in cascade to provide segmented digital-to-analog conversion of the general kind described above.
Another form of segmented CMOS digital to analog converter is described in a paper by M Tuthill, Analog Devices B. V. of Limerick, Ireland (date unknown). This describes a segmented converter in which the nodes of a resistive voltage divider are connectable via respective switches to two voltage rails, alternate nodes being connectable to respective rails, and the voltage segment obtained thereby is coupled by means of buffer amplifiers to an R/2R digital-to-analog converter.
Dingwall et al., in IEEE Journal of Solid State Circuits, Volume SC-20, No. 6, December 1985, describe an intermeshed ladder network in which a coarse ladder and a multiplicity of fine ladders are used to provide two-stage analog-to-digital conversion.
Cascaded ladder networks are also proposed for use in an analog-to-digital converter by Grant et al., IEEE Journal of Solid State Circuits, Volume SC-22, No. 2, April 1987. This paper describes the use of a coarse ladder network which is connected through buffer amplifiers to a fine ladder network both of which are arranged in association with a multiplicity of comparators to form a two-stage `flash` converter.
The main problem which arises from the use of a segmented converter is that if the fine converter is connected directly to the preceding relatively coarse converter, it will sink current which would otherwise flow through the coarse converter. This sinking of current affects the linearity of the conversion. The Post et al reference mentioned above illustrates a realisation in which there is no interface between the coarse and fine ladders. However, although the realisation provides monotonicity of the transfer curve, the integral linearity is poor.
Consequently, as described in the Grant et al., and Tuthill references, an interface is employed between the ladder networks. This interface normally comprises an operational amplifier configured as a buffer. As is well known, an operational amplifier has, effectively, an infinite input impedance and does not sink current, that is to say does not load the network to which the input is connected. However, there are two main drawbacks to the provision of such an interface. The response of an operational amplifier, and particularly a CMOS operational amplifier, is very slow compared to the settling time of a resister converter and tends to have, since the amplifier normally needs to be directly coupled, a large offset which affects the linearity of conversion. The Tuthill reference noted above describes a technique which tries to avoid any degradation of the monotonic response due to the offset but the technique does not preserve integral linearity.
Accordingly, it is an object of the present invention to provide an improved cascaded resistive network for use in digital-to-analog or analog-to-digital conversion.
It is a further or alternative object of the invention to provide an improved converter which does not require an interface between resistive ladder networks.
It is a further or alternative object of the invention to provided a segmented converter which is particularly suitable for realisation in CMOS technology.
Broadly speaking, the above objects may be attained by the provision of a current source which compensates for the sinking of current by the relatively fine divider. Such a current source may be coupled to lines which convey the voltage segment from the coarse divider to the fine divider and may be realised by a circuit which responds to a voltage developed across a part of the coarse voltage divider and includes means for comparing such a voltage with a current developed across a resistance corresponding to the resistance of the fine voltage divider to provide a controlled current generator which may coupled, for example by current mirrors, to the lines that connect a voltage segment to the fine divider.
Other objects and advantages of the invention will be apparent from a consideration of the following detailed description with reference to the drawings.